λ S→Y: Output function

ta S→Real: time advance function。

The atomic model consists of three sets and four functions。 The four functions in the seven-tuple, namely δint, δext, λ, and ta, are called the characteristic functions of an atomic model。 The atomic model of the DEVS formalism can be considered as a timed finite-state automata (FSA), and it is suitable for describing the behaviors of a device model。

Figure 3 shows a simple example of an automatic-guided vehicle (AGV) with two tasks, task 1(movement from p1 to p2) and task 2(movement from p2 to p1)。 As the two tasks should be triggered by external events, the virtual device model of the AGV must have two input ports, referred to here as X1 and X2 which are connected with the PLC output signals O_X1 and O_X2。 For this example, there are four states: S_P2, DO_TASK1, S_P1, and DO_TASK2。 While S_P2 and  S_P1

Fig。 3 An implementation procedure of a virtual device model (AGV)

p1 Task1:move from p1 to p2      p2

Task2:move from p2 to p1

I/O Signal table for an AGV

Device Signal Address Description

AGV O_T1 O1 Execute “Task1”

AGV I_T1 X1 Arrived at the Position “P2”

AGV O_T2 O2 Execute “Task2”

AGV I_T2 X2 Arrived at the Position “P1”

Output

M = < X, S, Y, intext, , ta> X:{ X1, X2};

S:{ S_P1*, DO_TASK1, S_P2, DO_TASK2  }

Y:{ Y1, Y2};

int  (DO_TASK1) = S_P2; int  (DO_TASK2) = S_P1

ext  (S_P1, X1 ) = DO_TASK11; ext  (S_P2, X2) = DO_TASK2

(DO_TASK1) = Y1; (DO_TASK2) = Y2

ta(S_P1)=ta(DO_TASK11)=    T1 ; ta(S_P2)=ta(DO_TASK2)= T2

take external events from the input ports for state transitions, DO_TAKS1 and DO_TASK2 take internal events that are the end events of the two tasks。 When the internal transition occurs from either DO_TAKS1 or DO_TAKS2, the output function sends a signal to the output ports (Y1 or Y2) that are connected to the PLC input signal (I_X1 or I_X2)。 Once the virtual device models are constructed, the virtual plant model can be defined by combining a set of virtual device models。 Then, the constructed virtual plant model can be used for PLC simulation to fix various errors that are not properly adjusted caused by control programming, as well as faults in the control programs。 We can minimize the stabilization time after the actual implementation, since most errors are fixed through the PLC simulation。 Since the virtual device model should be constructed manually in the modeling phase, much effort and in-depth knowledge of the simulation is necessary in this phase, which is a main cause of delays in the PLC simulation。 We propose an automated generation method of the virtual plant model by a reverse engineering approach for the PLC simulation, as shown in Fig。 4, to cope with the problem。 We separated the proposed implementation procedure into two phases, production system data collection phase, and an auto- mated generation phase。 In the data collection phase, we can easily obtain both log data (time-stamped signal history) and an I/O signal table from the existing production system。 Then, we can simply construct a set of virtual device models automati- cally by the proposed generating algorithm。 Since the obtained