7。 3。 4 Stress Analysis

There are two places in the Concept 1 package that warrant a stress analysis。 The first place is in

the ceramic substrate where it is being put into tension at the edge of the copper layer。 The

second place is in the solder layer at the outer edge of the semiconductor die。

With DBC, the substrate layer is put under considerable stress due to the CTE mismatch between

the ceramic substrate and the copper metallization layer。 DBC is provided with options for many

different material layer thicknesses to satisfy several requirements。 It is important to satisfy the

current carrying requirements with the thinnest layer of copper as possible, and to satisfy the heat transfer requirements with the thickest layer of ceramic possible。

(图)

Figure 7。 Concept 1-3D Thermal Prole

As noted earlier, DBC is offered with a choice of two different ceramics to use as the substrate

AIN and alumina。 One of the objectives is to use the thermal stress analysis to provide guidance

in choosing one of these materials over the other。

Substrate analysis method。 A 2D FEA was done on the cross section of a single die mounted on

the DBC metalized substrate。 The model was meshed in such a way as to provide a mesh density

Of roughly 200 nodes/mm along the interface between the upper copper pad and the substrate。

This is the location where a crack in the substrate will likely form and start growing to cause the

package to fail。 At this node density, the stress solution can be assumed to have less than 5%

error according to a mesh resolution study done previously。

A thermal analysis is first carried out with an appropriate heat load for a 60-kw SIC converter

put onto the die, and an appropriate convection coefficient on the underside of the package,

sufficient to keep the maximum temperature of the package below 300 °C。 The solution of the

thermal problem is then used as the load condition for the stress analysis。 The ceramic substrate

is assumed to fail in a brittle way, so the maximum principle stress criterion is applied to a plot

of the first principle stress。

Stress analysis results。 Figure 8 shows the first principle stress plot in the region of the substrate

at the copper metallization edge。 For the AIN substrate of 1 mm thickness and a copper layer of

0。 127 mm, the maximum principle stress along the interface between the copper and the

AIN。 For the alumina substrate of the same thickness。 The maximum principle stress in the same

area was 174 MPa。 This was below the tensile strength of 99% alumina of 207 MP, but with a

lesser margin。 The stress can be reduced in alumina by increasing the thickness of the substrate

layer, but the penalties brought about by the low conductivity of alumina are felt more。 One mm

is the maximum thickness offered for AJN, and 0。 127 mm is the minimum thickness for the

copper layer in commercial DBC, so the stress levels of the AIN DBC are at the minimum。

Thermal stress analysis on solder layer。 The solder layer is made up of gold-silicon eutectic

solder。 Because the CTE of the SIC semiconductor die ind the DBC are different it is expected

that significant stress will develop at the edge of the solder layer, possibly causing failure。

Solder layer analysis method。 For the solder layer analysis, the mesh node density is set to 200

nodes/mm in the solder layer to obtain an error of less than 5%。 The solder layer is assumed to be fillet prevents a nonphysical discontinuity in the von Mises stress at the corner between the

solder layer and the copper layer。 The thermal stress analysis is then carried out in the same way