基于FPGA的数字延迟线设计
摘要数字延迟线是对接收到的信号进行一段时间的整体延迟的原件或器件，随着超大规模、高速集成电路的快速发展，数字系统所要求的集成度不断提高，运算的速度也在加快，因此，时钟延迟和时钟偏远对系统性能的影响越来越显著，而数字延迟线则可以降低这种时钟偏远，从而满足FPGA的各种时序需要，因此数字延迟线的应用越来越广泛。
首先，对各种延迟线的设计方法进行了总结归纳，通过对其优缺点的比较得出最优方案，在此基础上选择了FIFO存储器的方法。然后对设计该数字延迟线所需要的知识点以及其各模块的原理进行了阐述，通过阅读相关的书籍资料，了解了了解芯片AD9461,AD9777, IDT72V36110的特性，在FPGA基础上提出了数字延迟线的各个模块的设计思路，最后，应用Verilog语言进行编程，完成了对数字延迟线的各个模块的设计，从而实现了输入信号的延迟。通过对程序的仿真，得到了相应的时序图，验证了实验结果的准确性，从而说明了这种方法设计简单，延迟精度高，工作稳定可靠，值得采用。61689
毕业论文关键字： 数字延迟线；FPGA；FIFO
毕业设计说明书（论文）外文摘要
Title Design of the digital delay line based on FPGA
Abstract The digital delay line is a device which makes the received signal delay for a period of time, with the rapid development of integrated circuit of very large scale and high speed, the requirement of digital system integration improves constantly. as a result, the influence of the clock delay and clock remote to the performance of the system is more and more significant, while the digital delay line can reduce the clock remote to meet the needs of the various FPGA, so the application of the digital delay line is more and more wide.
Firstly, the design method of all sorts of delay line are summarized in this paper, by comparing their advantages and disadvantages, the optimal solution is got, on the basis, we find the FIFO memory method is the best choice. Secondly, the knowledge and expatiates on the principle of each module needed for the design is introduced, by reading the relevant books, we know the features of the chip AD9461, AD9777, IDT72V36110, based on FPGA the design of modules of digital delay line is put forward. In the end, by the programming with the Verilog language, the design of the various modules of the digital delay line is completed, so as to realize the four switches of the delay time. Through the process of simulation, we obtain the corresponding sequence diagrams, verify the accuracy of the experimental results which shows this method is simple in design, stable and reliable in work ,of high precision, and is worth using.
Keywords: digital delay line； FPGA；FIFO
1 引言 1
1.1课题研究背景与意义 1
1.3本文主要工作与内容安排： 2
2 延迟线原理 3
2.1数字延迟线概述 3
2.2采样原理与采样恢复 4
2.3本章小结 6
3 数字延迟线设计 6
3.1 ADC模块 8
3.2 DAC模块 9
3.3 FIFO模块 14
3.4本章小结 15
4 数字延迟线的软件实现