Counter-comparator is one simple method to achieve digital-to-time conversion in DPWM。  This architecture uses a cycling counter and a comparator by setting a set-reset (SR) latch “high” when the counter value is zero and “low” when the counter reaches the control duty ratio。  This scheme has the advantage of simple structure and excellent linearity in the digital-to-time conversion。  According to (12), a clock of 2N·fs is needed to achieve an N-bit DPWM at switching frequency fs。  However, when it operates at the high frequency fs, it falls into the drawback of ultra-high frequency clock。  Thus, the counter-comparator is usually used as the solution for few-bit MSBs inside DPWM architectures。 

Linked to the MASH ∆-Σ block and segmented DCM phase-shift block above, a 2-bit counter-comparator block shown in Fig。 9 is used in the proposed DPWM。  It includes a 2-bit counter-comparator and a FDP (D Flip-Flop with Asynchronous Preset)。  D[5:4] and Sc respectively come from previous MASH ∆-Σ block and segmented DCM phase-shift block。 

D。 Operation of the Hybrid ∆-Σ DPWM 

With a combination of the three blocks described above: MASH ∆-Σ modulator, segmented DCM phase-shift block and counter-comparator block, the completed Hybrid ∆-Σ DPWM architecture can be figured in Fig。 10。 

Fig。 9。 2-bit counter-comparator block linked to MASH ∆-Σ block and segmented DCM phase-shift block。 

In the FPGA implementation, the 11-bit DPWM signal with 4MHz switching frequency is realized by the proposed Hybrid ∆-Σ DPWM architecture。  Among the 11-bit DPWM, 5 bits are implemented by MASH ∆-Σ modulator, 4 bits are achieved by segmented DCM phase-shift block (NDCM=4), and 2 bits are generated by counter-comparator (NDPWM=2)。  According to (12) and (13) respectively, the DPWM counter clock is FCLK=22·fs and the clock for DCM phase-shift is  FDCM=22·FCLK=24·fs。  With the switching frequency of fs=4MHz, FCLK is merely 16MHz and FDCM is 64MHz。  Hence, the proposed Hybrid ∆-Σ DPWM can dramatically alleviate the clock requirement and allows operation with low power consumption。 

An example is employed to explain the operation procedure: Supposing the nth-cycle duty value from the control algorithm is d(n)=10010101010b, feedback value e1(n–1)=0101010b and e2(n–1)=01010b in ∆-Σ modulator, then the new duty D(n)=100110b is generated。  D[5:4]=10b is implemented by the 2-bit counter-comparator, D[3:2]=01b is used to select phase-shifted clock PX90 for S1, and D[1:0]=10b is set to select phase-shifted clock PY180 for S2。  Through the logic AND operation of S1 and S2, the final phase-shifted signal Sc is obtained and sent to FDP to change PWM signal。  The logic waveforms of the example operation are shown in Fig。 11。 

III。 SIMULATION AND EXPERIMENTAL RESULTS 

Besides the Hybrid ∆-Σ DPWM architecture, the digital controller also includes a classical PID control algorithm module。  The PID algorithm is designed by Matlab/Simulink and the whole digital controller is implemented by the XC2VP30 FPGA。 

A。 Modeling of Digital PID-Controlled Buck Converter 

The transfer function of the buck converter can be gained by averaging state-space method and small-signal analysis in continuous current mode (CCM)。  Transfer the equations into z-domain, the buck converter G(z) and the classical PID control KPID(z) can be written as [15]: 

    G z( ) = b z b1 + 2 z2 +a z a1 + 2

2 + + 0( 2 + r1 z+ r2 ) ,    (14) r z

r z0 r z r1 2 = r0