KPID ( )z = (z−1)(z s+ 1) (z−1)(z s+ 1)

where a1, a2, b1 and b2 are determined by the parameters of buck converter, while r0, r1, r2 and s1 are the PID controller parameters to be determined。  By cancelling the poles of G(z) with the zeros of KPID(z), the closed-loop reference for the output voltage transfer function is: 

Γ= Vout = KPID ( ) ( )z G z

Vref 1+KPID ( ) ( )z G z ,  (15) 

  = r b z r b0 1 + 0 2 = r b z r b0 1 + 0 2

z2 + − +(s1 1 r b z0 1) +(r b0 2 −s1) z2 + p z1 + p2

where p1 and p2 are determined by the desired closed-loop performance, which corresponds to second-order dynamics with a resonant frequency ω and a damping ratio ζ。  Finally the parameters are determined as 

r0 = + +(1 p1 p2) (b1+b2), 。        (16) 

r1 = a r r1 0 2, = a r s2 0 1, = r b0 2 − p2

In this case, the discrete low-power buck converter has the parameters as follows, L=4。7μH, C=22μF, R=5Ω, Vin=3。3V, Vout=1。5V, fs=4MHz; PID control dynamics are ζ=0。7 and ω is set to 15 times the open-loop pulsation one。  As a consequence, the PID controller parameters are obtained: r0 = 141。5872, r1=–281。6306, r2=140。1043 and s1 =–0。7959。 

The time-domain behavior of the digitally controlled system is studied using Matlab/Simulink, where the buck converter is modeled as a hybrid model [16]。  The ADC model has a 10-bit resolution and DPWM model has an 11-bit resolution, which meets the condition of non-limit cycle [9]。  All the calculations are computed in fixed-point data form and the effects of delay and quantization are all taken into account in the simulation。 

Fig。 12 shows the power spectral density of the MASH Δ-Σ modulator (shown in Fig。 5)。  It can be seen that the MASH Δ-Σ DPWM modulator has a good noise-shaping ability as the noise density is kept at –40dB when operation frequency towards to fs。   

B。 FPGA-Implementation 

The implementation of the proposed digital controller (11-bit Hybrid Δ-Σ DPWM and PID algorithm module) is performed on an XC2VP30 FPGA board。  The proposed 11-bit DPWM operating at frequency up to 4MHz requires 

internal clock FDCM=64MHz for DCM phase-shift block and hardware clock FCLK=16MHz for counter。  Compared with the maximum speed of signal process in FPGA, FCLK and FDCM required in this DPWM are very low。 

The timing-simulation results of the segmented DCM phase-shift block (shown in Fig。7) are illustrated in Fig。 13, where fs=4MHz, FDCM=64MHz, FCLK=16MHz with an example ratio of D[5: 0]=100011b (ratio 50%)。 

Finally, the timing-simulation waveforms of the complete 11-bit FPGA-based Hybrid Δ-Σ DPWM is shown in Fig。 14 with an example ratio of D[5:0]=100011b。 

Fig。 13。 Timing-simulation waveforms of 4-bit segmented DCM phase-shift。 

C。 Experimental Verification 

  To experimentally verify the functionality of the proposed digital controller for the high-frequency low-power SMPS, a discrete synchronous buck converter with 3。3V input and 1。5V output voltage is fabricated and the switching frequency is fs=4MHz。  The voltage feedback is performed by a 10-bit A/D converter AD9203。  The A/D device is probably a high energy consumption block in the system, which remains an effort-consuming task in the case of ASIC implementation of the digital controller。  This issue is not discussed here。  The block diagram of the test platform is shown in Fig。 15, and the parameters of the digital controller are given in Table I。