摘要频率综合器是以高精度晶体振荡器作为基准，通过合成技术产生一系列具有一定频率间隔的高精度频率源，分直接合成（DDS）和锁相环合成(PLL)两种。

    直接数字频率合成(DDS)技术采用的合成方法是全数字的，所产生的信号具有频率分辨率高、频率切换速度快、频率切换时相位连续，输出相位噪声低和可以产生任意波形等优点；但同时输出范围有限，以及输出杂散较大的局限。锁相环（PLL）合成法通过锁相环完成频率的加、减、乘、除运算。该方法结构简化、便于集成，且频谱纯度高，目前使用比较广泛。64989

    本文将以毫米波频率步进雷达频率综合器为研究对象，分析并研究锁相环的工作原理。并深入对锁相环的噪声模拟、调频频率综合器的调频时间(FM)进行计算与推理。

    频率综合器以可编程门阵列（FPGA）为主要控制电路芯片，运用VHDL编程语言实现频综的同步控制信号。

毕业论文关键词：频率综合器（频综）、FPGA、VHDL、频率步进雷达、锁相环（PLL）

毕业设计说明书（论文）外文摘要

Title

FPGA-based frequency synthesizer Timing Control Design

Abstract

Frequency synthesizers is high-precision crystal oscillator as a benchmark, through synthetic technology to produce a series of high precision frequency source with certain frequency interval, points directly synthesis (DDS) and phase-locked loop (PLL) two kinds.

Direct Digital Synthesis (DDS) technology uses digital synthesis method, the resulting signal has a high frequency resolution, frequency switching speed, phase-continuous frequency switching time, low phase noise output and can generate arbitrary waveforms, etc; But the limited output range, and the output spurious large disadvantage.PLL synthesis (PLL) frequency through complete phase-locked loop to add, subtract, multiply and pide operations. This method simplified structure, easy integration and high spectral purity, more widely used.

This paper will millimeter wave radar frequency synthesizer frequency step for the study, analysis of phase-locked loop works. And in-depth on the PLL noise analog, FM frequency synthesizer FM time calculated reasoning.

Frequency synthesizer with programmable gate array (FPGA)-based control circuit chip, the use of VHDL programming language synchronization control signal frequency synthesizer.

Key Words:    Frequency synthesizer    FPGA     VHDL

                Stepped Frequency Radar      PLL

目 次

1 绪论…………………………………………………………………………………1

1.1 频率综合器的概述………………………………………………………………1

1.2 频率合成技术……………………………………………………………………1

1.3 FPGA简介…………………………………………………………………………2

1.4 VHDL语言简介…………………………………………………………………3